Anonymous
May 9, 2023
How do I answer this question describe below?
Assume that one 16 bit and two 8 bit microprocessors are to be interfaced to a system bus. The following details are given:
(1) All microprocessors have a 16 bit address bus.
(2) All microprocessors have the hardware features necessary for any type of data transfer: programmed I/O, interrupt driven I/O, and DMA.
(3) Two memory boards, each of 64 Kbytes are interfaced with the bus. The designer wishes to use a shared memory that is as large as possible.
(4) The system bus supports a maximum of four interrupt lines and one DMA line. Make any other assumptions necessary and:
(a) Give the system bus specifications in terms of number and types of lines.
(b) Describe a possible protocol for communicating on the bus.
(c) Explain how the aforementioned devices are interfaced to the system bus.
(1) All microprocessors have a 16 bit address bus.
(2) All microprocessors have the hardware features necessary for any type of data transfer: programmed I/O, interrupt driven I/O, and DMA.
(3) Two memory boards, each of 64 Kbytes are interfaced with the bus. The designer wishes to use a shared memory that is as large as possible.
(4) The system bus supports a maximum of four interrupt lines and one DMA line. Make any other assumptions necessary and:
(a) Give the system bus specifications in terms of number and types of lines.
(b) Describe a possible protocol for communicating on the bus.
(c) Explain how the aforementioned devices are interfaced to the system bus.
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Anonymous
May 10, 2023
(a) Based on the given details, the system bus specifications in terms of number and types of lines are:
- Address bus width: 16 bits for all microprocessors.
- Data bus width: 8 bits for each 8-bit microprocessor and 16 bits for the 16-bit microprocessor.
- Interrupt lines: Maximum of four interrupt lines.
- DMA line: One DMA line.
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Anonymous
May 10, 2023
(b) A possible protocol for communicating on the bus could involve the following steps:
- A microprocessor requests access to the bus by asserting a bus request signal.
- The bus controller grants access to the requesting microprocessor by asserting a bus grant signal.
- The requesting microprocessor places the desired address and data on the appropriate bus lines.
- The other microprocessors on the bus monitor the address lines to determine if the requested address is intended for them.
- If the address matches the monitoring microprocessor's address, it asserts a bus acknowledge signal to indicate that it will handle the request.
- The requesting microprocessor transfers the data to or from the appropriate memory location or I/O device.
- The handling microprocessor releases the bus by deasserting the bus acknowledge signal.
- The bus controller releases the requesting microprocessor by deasserting the bus grant signal.
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Anonymous
May 10, 2023
(c) The devices are interfaced to the system bus as follows:
- Each microprocessor is connected to the bus via its address and data lines, as well as the bus request and grant lines.
- The memory boards are connected to the bus via their address and data lines, as well as control lines for read and write operations.
- The interrupt lines are shared among all devices on the bus, with each device assigned a unique interrupt request line.
- The DMA line is shared among all devices on the bus, with each device assigned a unique DMA request line. When a DMA transfer is requested, the DMA controller takes over the bus and transfers the data directly between memory and the I/O device without intervention from the microprocessor.
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